In the fabrication of semiconductor devices, such as fin field effect transistors (FinFETs), there is typically a need to etch identical fins at well-defined locations in the wafer. However, if the final fin pattern is directly formed in the wafer by using a hard mask presenting that same pattern, not all fins etched in the wafer through that hard mask will be identical. For instance, when a fin pattern comprising several groups of closely packed fins is first defined in a hard mask and then transferred into the wafer, the fins at the edges of a group will etch differently than the inner fins of the group. One method commonly used to get around this issue is to first form a large group of closely packed parallel fins in a wafer via a matching hard mask, followed by selectively removing from that large group all fins that do not belong to the final fin pattern. This way, the problem is limited to the edge of the large group only.
Such fin removal, which is for example described in U.S. Pat. No. 9,209,037B2, is challenging due to the very small fin pitch that is present for advanced nodes. Not only does this impose stringent conditions on the mask pattern that needs to be formed; the cut lithography additionally becomes very challenging in terms of the overlay requirements, where small overlay errors may remove desired fins and/or leave parts of undesired fins. This results in increasing patterning costs as scaling is further increased, requiring for example expensive EUV or 193i multi-patterning techniques.
As such, there is still a need for improved methods of removing undesired fins.